Table of Contents

2017 Month : June Volume : 3 Issue : 2 Page : 27-29

STRUCTURAL ANALYSIS OF VEDIC MULTIPLIER USING URDHVA-TIRYAKBHYAM SUTRA ALGORITHM FOR FPGA.

Saktiprasanna Swain1, Subhashree Samal2, Manoj Kumar Sahoo3

Corresponding Author:
Manoj Kumar Sahoo,
M-Tech. Student,
Department of Electronics and Communication Engineering,
BPUT, Rourkela, Odisha.
E-mail: mksahoo@hotmail.com, mailymksahoo@gmail.com

 

ABSTRACT

This paper proposes the design of high speed Vedic multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. A high-speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. Vedic Mathematics has a unique technique of calculations based on 16 sutras. This paper presents study on high speed 8x8 bit Vedic multiplier architecture, which is quite different from the conventional method of multiplication like add and shift. Further, the Verilog HDL coding of Urdhva-Tiryakbhyam Sutra for 8x8 bits multiplication, squaring circuit as application and their FPGA implementation by Xilinx ISE Tool on Spartan-3E kit have been done and output has been displayed on LEDs of Spartan 3E FPGA board.

 

KEYWORDS

FPGA, Architecture, Multiplication, Vedic Mathematics, Vedic Multiplier.

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